This application claims the benefit of Korean Patent Application No. 2002-0037852, filed Jul. 2, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
The present invention relates to methods of forming semiconductor devices and, more particularly, to methods of forming dual gate semiconductor devices.
A conventional transistor may include a gate electrode formed on an active region of a semiconductor substrate, a gate insulating layer interposed between the gate electrode and the substrate, and source/drain areas formed in an active region adjacent to opposite sides of the gate electrode. The gate insulating layer may be a silicon oxide layer, such as a thermal oxide, and the gate electrode may be doped polysilicon.
With trends toward increased integration of semiconductor devices, gate insulating layer thickness and wiring widths are likely to continue to decrease. Decreased gate insulating layer thickness may lead to increased leakage current, and reduced wiring widths may lead to increased resistance of the gate electrode.
Attempts to suppress leakage current have been made. In one such attempt, a gate insulating layer was formed from a high-k dielectric material, compared to a typical silicon oxide. It may thereby be possible to form a gate insulating layer having a greater thickness, compared to a gate insulating layer of silicon oxide, which may suppress a leakage current.
Attempts to suppress increases in the resistance of the gate electrode have also been made. In one such attempt, a gate electrode was formed from a metal having a lower resistivity than doped polysilicon. Unfortunately, when such a metal gate electrode is formed on a high-k dielectric layer, the metal layer may be oxidized by the high-k dielectric layer, and associated transistor characteristics may be deteriorated.
Transistors in semiconductor devices may be classified as NMOS transistors and PMOS transistors based upon the main carriers that migrate through their channel. The main carriers of the NMOS transistor are electrons, and those of the PMOS transistor are holes. A work function of a PMOS gate electrode in a PMOS transistor is higher than that of an NMOS gate electrode in a NMOS transistor. The different work functions of PMOS and NMOS transistors may increase their fabrication complexity.
A conventional method of forming a dual gate is explained with reference to FIGS. 1-3. Referring to FIG. 1, a process well known in the art may be used to form device isolation layers 2, and P-type and N-type active regions 3 and 4 defined by the device isolation layers 2. An NMOS gate insulating layer 5 and an NMOS gate electrode layer 6 are sequentially stacked on a semiconductor substrate 1 having the P-type and N-type active regions 3 and 4.
Referring to FIG. 2, the NMOS gate electrode layer 6 and the NMOS gate insulating layer 5 are successively patterned to form an NMOS gate electrode 6a. The NMOS gate electrode 6a is disposed over the P-type active region 3. A PMOS gate insulating layer 7 and a PMOS gate electrode layer 8 are sequentially stacked on the semiconductor substrate 1 and the NMOS gate electrode 6a. A work function of the PMOS gate electrode layer 8 is higher than that of the NMOS gate electrode 6.
Referring to FIG. 3, the PMOS gate electrode layer 8 and the PMOS gate insulating layer 7 are successively etched to form a PMOS gate electrode 8a over the N-type active region 4. The NMOS gate electrode 6a may become damaged, thereby deteriorating one or more characteristics of an NMOS transistor formed therewith.
When the NMOS and PMOS gate electrodes 6a and 8a are formed using a damascene process (not shown), the fabrication process may become more complex.
A method of forming a dual gate electrode that may be used in a CMOS circuit is disclosed in U.S. Pat. No. 6,027,961, entitled xe2x80x9cCMOS SEMICONDUCTOR DEVICES AND METHOD OF FORMATIONxe2x80x9d to Maiti et al. As disclosed, a gate insulating layer and a tantalum layer are sequentially formed over a semiconductor substrate. Nitrogen ions are selectively implanted into a tantalum layer on a PMOS transistor region to form a first tantalum nitride layer. The nitrogen ions are selectively implanted into a tantalum layer over an NMOS transistor region to form a second tantalum nitride layer whose work function is lower than that of the first tantalum nitride layer. Because a lower side of the tantalum layer contacts the gate insulating layer, the lower side may be oxidized during an annealing process for activating the nitrogen ions. As a result, the characteristic of a transistor may be deteriorated.
Another method of forming a dual gate electrode that may be used in a CMOS circuit is disclosed in Japanese Laid-open Patent No. 2001-217323. As disclosed, a tantalum pentoxide (Ta2O5) layer is formed on a semiconductor substrate. Using a nitrogen plasma process, the tantalum pentoxide layer is nitrified to form a thin tantalum nitride layer on a surface of the tantalum pentoxide layer. There is a restriction that the gate insulating layer must be made of a tantalum-containing insulator. Moreover, there is a limitation on an increase in the thickness of the tantalum nitride layer. However, if the thickness of the tantalum nitride layer is not sufficient, it may be difficult to obtain acceptable transistor characteristics because of a work function of the tantalum nitride layer.
A method for forming a dual gate is provided according to embodiments of the present invention. A semiconductor substrate is provided that has a first region of a first conductivity type and a second region of a second conductivity type. A gate insulating layer is formed on the semiconductor substrate. An initial metal nitride layer is formed on the gate insulating layer, opposite to the semiconductor substrate. Nitrogen ions are implanted into the initial metal nitride layer in the second transistor region to form a nitrogen-rich metal nitride layer. The initial metal nitride layer is patterned to form a first gate electrode in the first region. The nitrogen-rich metal nitride layer is patterned to form a second gate electrode in the second region. The work function of the nitrogen-rich metal nitride layer is higher than that of the initial metal nitride layer.
According to further embodiments of the present invention, the first region may be an NMOS transistor region, the second region may be a PMOS transistor region, the first gate electrode may be an NMOS transistor gate electrode, and the second gate electrode may be a PMOS transistor gate electrode. The initial metal nitride layer may be patterned at the same time as (concurrent with) the nitrogen-rich metal nitride layer. The gate insulating layer may be formed from a high-k dielectric material whose dielectric constant is greater than that of silicon oxide. A silicate layer may be formed on the semiconductor substrate before the gate insulating layer is formed.
According to yet further embodiments, the metal layer and the initial metal nitride layer may be patterned to form an initial metal nitride layer pattern and a first metal layer pattern that are stacked in the first transistor region, and the metal layer and the nitrogen-rich metal nitride layer may be patterned to form a nitrogen-rich metal nitride layer pattern and a second metal layer pattern that are stacked in the second transistor region.
According to other embodiments of the present invention, a method of forming a dual gate includes providing a semiconductor substrate having a first region of a first conductivity type and a second region of a second conductivity type. A mold insulating layer is formed on the semiconductor substrate. The mold insulating layer is patterned to form a first gate groove in the first region of the semiconductor substrate and to form a second gate groove in the second region of the semiconductor substrate. A gate insulating layer is formed on the semiconductor substrate and the first and second gate grooves. An initial metal nitride layer is formed on the gate insulating layer, opposite to the semiconductor substrate, and filling the first and second gate grooves. The initial metal nitride layer is planarized to form a first gate electrode in the first gate groove and a backup second gate electrode in the second gate groove. Nitrogen ions are implanted into the backup second gate electrode to form a second gate electrode. A work function of the second gate electrode is higher than that of the first gate electrode.
According to further embodiments of the present invention, the first region may be an NMOS transistor region, the second region may be a PMOS transistor region, the first gate electrode may be an NMOS transistor gate electrode, and the second gate electrode may be a PMOS transistor gate electrode. A silicate layer may be formed on the semiconductor substrate and the first and second gate grooves, and the gate insulating layer may then be formed on the silicate layer. The gate insulating layer may be formed from a thermal oxide on the exposed areas of the first and second transistor regions. The backup second gate electrode may be annealed after the nitrogen ions are implanted. The gate insulating layer and the mold insulating layer may be anisotropically etched, using the first and second gate electrodes as masks, after the nitrogen ions have been implanted into the backup second gate electrode.